This application claims the benefit of Korean Application No. P97-19027, filed in Korea on May 16, 1997, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to a driving circuit for driving the LCD.
2. Discussion of the Related Art
Cathode ray tubes (CRTS) are widely used in display devices for television sets and display monitors for computers, because a CRT can easily reproduce color and it has high respond speed. However, CRTs are too large, heavy and consume too much power to be portable. Because of this, it is desirable to replace the CRT with other types of display. To overcome the above mentioned disadvantages of the CRT, a considerable amount of research and development has been conducted to design alternative types of display, such as liquid crystal displays, plasma display panels, and so on. Among them, a liquid crystal display is one of the most generally used devices because the LCD does not have the bulky electron gun like the CRT, and the LCD can be applied to a thin television set to be mounted on the wall. Furthermore, the LCD can be applied to a portable display device, such as a note-book computer, because the power consumption is very low, and accordingly, the LCD can be driven by a battery.
The schematic structure of a conventional LCD is shown in FIGS. I and 2. FIG. 1 shows 20 the perspective view, and FIG. 2 shows the structure of the lower panel. The LCD includes an upper panel 21, which has a polarization plate 20, a color filter 22, and a common electrode 23; a lower panel 25, which has thin film transistors (TFTs) 13 and pixel electrodes 26; and a liquid crystal material 24 inserted between the upper panel 21 and the lower panel 25. The lower panel further includes a plurality of scan lines 14 and a plurality of data lines 15. The scan lines 14 and the data lines 15 perpendicularly cross each other. At the area surrounded by the neighboring scan lines and data lines, the pixel electrode 26 is formed. At each of the intersections of the scan lines and data lines, the TFT 13 is formed. Each of the area surrounded by the neighboring scan lines and data lines is called a pixel. Thus, the pixel includes the pixel electrode 26, the common electrode 23, and the liquid crystal material 24 in between. In addition, the lower panel 25 further has a data driver IC 11 connected to the data lines 15 and a scan driver IC 10 connected to the scan lines 14 (FIG. 2).
The TFT includes a gate electrode, a source electrode and a drain electrode. The gate electrode is connected to the (an line, the source electrode is connected to the data line, and the drain electrode is connected to the pixel electrode. The drain electrode and the source electrode are connected with a semiconductor layer of the TFT. The TFT works as a switch that passes a data voltage applied to the data line to the drain electrode when a scan voltage is applied to the gate electrode through the scan line. The data voltage applied to the drain electrode is in turn applied to the pixel electrode connected to the drain electrode.
Video data are applied from a controller 17 to the data driver IC 11. The video data include grey scaled data of red (R), green (G), and blue (B), which are applied to the corresponding pixel electrodes 26. The data driver IC 11 latches the video data, which come from the controller IC 17, until all the data of one line are inputted. Then, the video data of one line is transferred to the data line, one at a time. At that time, the scan driver IC 10 applies a scan voltage to the scan line 14 connected to TFTs 13 to reproduce the video image at the pixel electrodes 26 according to the scan signal of the controller 17.
When the scan voltage is applied to a scan line, the TFTs connected to the scan line are turned on. Accordingly, the video data applied to the data lines are sent to the pixel electrodes through the TFTs. Therefore, a voltage is applied to each pixel electrode. On the other hand, constant voltage is applied to the common electrode. Accordingly, a voltage difference is formed between the pixel electrode and the common electrode, and an electric field is formed by the voltage difference. The arrangement (or orientation) of the liquid crystal molecules between the pixel and common electrodes is changed according to the electric field, and the amount of light transmission at the pixel is modulated. That is, there are differences in light transmission at the pixels applied with a data voltage and the pixels not applied with a data voltage. Using these properties of pixels, the LCD works as a display device.
Since there are many data lines in the LCD in general, a plurality of data drivers are necessary, as shown in FIG. 3. The plurality of the data driver ICs are connected to the controller IC 17 via a bus line 18. The data driver ICs 11xe2x80x2 latch the sequentially applied video data, until video data for one line are all inputted. Then, these one-line data are sent to the data lines 15 at one time. As the number of data lines increases, a faster clock signal is required for each controller IC. That is, the frequency of the clock signal of the controller IC needs to be higher in high resolution LCD panels. As a result, the high frequency of the clock signal is one of the causes of increasing the electrical load at the controller IC and the peripheries.
To solve the problem associated with the high frequency clock signal, a divided driving method, as shown in FIG. 4, and a double bank driving method, as shown in FIG. 5, have been used for sending video data to the data driver IC.
In the divided driving method shown in FIG. 4, the data driver ICs are divided into two groups A and B, and the video data are sent to and latched at the two groups. When the video data for the first line (the first row of pixels) are applied to the controller IC 17, the controller IC 17 stores the video data for the group A and the group B in a memory. When the video data for the second line (the second row of pixels) are applied to the controller IC 17, the stored first line data are simultaneously sent to the groups A and B of data driver ICs 30, 31, respectively. Therefore, the frequency of the clock signal can be made half of that for the LCD of FIG. 3.
In the double bank driving method shown in FIG. 5, the data driver ICs are divided into two groups. One group, an odd data driver IC group 32, is the driver for ICs connected with the odd numbered data lines; the other group, an even data driver IC group 33, is for the driver ICs connected to the even numbered data lines. The driver ICs are disposed at both sides of the panel. This way, the frequency of the clock signal can be made half of that for the LCD shown in FIG. 3.
However, in the divided driving method, it is necessary to install a number of memories for storing the video data. This is especially true for a high resolution LCD, which requires a large number of data lines, which in turn requires a large capacity in the memory for storing the video data. In the double bank driving method, since the driver ICs are disposed at the two sides of the panel, the visible area of the display panel is smaller than that for the single bank mode in which the driver ICs are disposed at only one side of the panel. Furthermore, in the COG (Chip On Glass) technique, the above mentioned problems are more serious.
Accordingly, the present invention is directed to a driving circuit for a liquid crystal display that substantially obviates the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an improved driving circuit for a liquid crystal display that has a low power consumption and a small occupation area.
Another object of the present invention is to provide an improved driving circuit for a liquid crystal display in which the frequency of the clock signal is less than half of the conventional driving circuit with a single bank mode structure.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a driving circuit for driving a liquid crystal display, including a clock generator processing a first clock signal to output a second clock signal, the clock speed of the second clock signal being half of that of the first clock signal; a memory for storing a first video data and a second video data in accordance with the first clock signal; and a data controller for simultaneously outputting the first video data and the second video data stored in the memory in accordance with the second clock signal.
In another aspect, the present invention provides a driving circuit for driving a liquid crystal display, including a clock generator processing a first clock signal to output a second clock signal, the clock speed of the second clock signal being a third of that of the first clock signal; a memory for storing a first video data, a second video data, and a third video data in accordance with the first clock signal; and a data controller for simultaneously outputting the first video data, the second video data, and the third video data stored in the memory in accordance with the second clock signal.
In another aspect, the present invention provides a driving circuit for driving a liquid crystal display, including a clock generator for processing a first clock signal to output a second clock signal, the clock speed of the second clock signal being one Nth of that of the first clock signal with N being a positive integer; a memory for storing N sets of video data in accordance with the first clock signal; and a data controller for simultaneously outputting the N sets of video data stored in the memory in accordance with the second clock signal.
In another aspect, the present invention provides a driving device for driving a liquid crystal display in accordance with an input video signal, the driving device including a memory having a plurality of memory areas; and a data processor serially sampling the input video signal in accordance with a first clock signal to temporarily store the sampled video signal in the plurality of memory areas of the memory, the data processor serially outputting the stored video signal concurrently from all of the plurality of memory areas in accordance with a second clock signal whose clock speed is slower than that of the first clock signal, the data processor constantly updating the data in the memory by the video signal that are being sampled while the previously stored video signal are being outputted from the memory.
In a further aspect, the present invention provides a liquid crystal display device displaying a video image in accordance with an input video signal, the liquid crystal display including a first substrate including a plurality of data lines, a plurality of scan lines substantially perpendicularly crossing with the plurality of data lines, a plurality of pixels electrodes each disposed at areas surrounded by the scan lines and data lines, and a plurality of thin film transistors each disposed at the respective intersection of the data lines and the scan lines, the gate of the thin film transistor being connected to the adjacent scan line, the source of the thin film transistor being connected to the adjacent data line, and the drain of the thin film transistor being connected to the adjacent pixel electrode; a second substrate opposite the first substrate; a liquid crystal material interposed between the first substrate and the second substrate; a memory having a plurality of memory areas; a data processor serially sampling the input video signal in accordance with a first clock signal to temporarily store the sampled video signal in the plurality of memory areas of the memory, the data processor serially outputting the stored video signal concurrently from all the plurality of memory areas in accordance with a second clock signal whose clock speed is slower than that of the first clock signal, the data processor constantly updating the data in the memory by the video signal that are being sampled while the previously stored video signal are being outputted from the memory; and a plurality of data drivers connected to the data lines for latching the video signal outputted from the data processor to simultaneously output pixel driving signals for one row of the pixels to the plurality of data lines on the first substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.